As semiconductor integrated circuits become more highly integrated, finer MOS type field effect transistors are manufactured by, for example, shortening the gate length. As gate electrodes become finer, the cut off between the source and the drain becomes difficult for field type transistors, such that short channel effects such as punch-through occur.
As one measure for reducing the short channel effect, there is a technique of forming an impurity (referred to as pocket area) at an outer side of a source area or a drain area (pocket injection technique). However, in a case where the gate is fabricated into a fine size with length no more than 30 nm, a pocket area at the outer side of the source area may overlap with a pocket area at the outer side of the drain area. This leads to a problem of increasing the impurity concentration at the channel part. Therefore, in a MOS transistor having a fine gate, it is desired to improve mobility while maintaining a low channel impurity concentration and also to reduce the short channel effect.
Accordingly, there is proposed a method of not forming a source extension area and a drain extension area (impurity area) but instead forming an inversion layer corresponding to these areas by using a fixed charge (see, for example, Japanese Laid-Open Patent Application No. 2005-175378). The source extension area is an impurity area extending toward a channel area formed in continuation with the source area. The drain extension area is an impurity area extending toward a channel area formed in continuation with the channel area.
The method shown in Japanese Laid-Open Patent Application No. 2005-175378 discloses a method of forming an inversion layer corresponding to these areas by using a silicon oxide film containing an impurity (e.g., cesium) as the fixed charge.
Furthermore, it is disclosed that the fixed charge used for forming the inversion layer may be fabricated by performing plasma nitradation on silicon (see, for example, G. H. Buh et. al, IEEE IEDM 2005). Accordingly, by using such a method of using the nitradated film, an inversion layer can be formed directly below the nitradated film (positive fixed charge). Thus, such an inversion layer can be used substantially as the source/drain extension area.
However, the method disclosed in Japanese Laid-Open Patent Application No. 2005-175378 is difficult to be applied to an actual process of manufacturing a semiconductor device for the reasons such as 1) it is difficult to perform ion injection while having the impurity contained only inside the silicon oxide film, 2) manufacturing cost becomes high due to separate ion injection for the NMOS and the PMOS in a photo-masking process, and 3) injection of special types of ions (e.g., cesium/barium) is required.
Meanwhile, the method disclosed in G. H. Buh et. al, IEEE IEDM 2005 has a problem of forming positive fixed charges also in the PMOS side in the same manner as the NMOS side by the plasma nitradation in a case of a CMOS configuration. In the PMOS side, since the conductivity type becomes opposite to the NMOS side, the inversion layer formed in the source/drain extension area may adversely affect the behavior of the transistor. In a case of a combination (CMOS) having NMOS and PMOS, this method using fixed charges may not be effective from the aspect of the behavior of the transistor.
In performing plasma nitradation on a substrate, it may be possible to mask the PMOS side with resist and form a nitride film containing fixed charges. However, considering the facts that 1) a plasma is used and 2) the temperature in performing plasma nitradation is high, it is difficult to actually perform such masking by using resist having an organic substance as its main component.